The present invention relates to an output power control circuit for a power amplifier circuit and, more particularly, to an output power control circuit for a power amplifier circuit which comprises an input amplifier and an output amplifier connected in series therewith.
Conventionally, there are various control methods for controlling the output power of power amplifiers: an input power control scheme; a power supply control scheme; a scheme for controlling constants of the amplifier circuit; and a scheme for directly controlling the output power with a variable attenuator. A proper control method is selected in consideration of various factors such as power, a power supply, a power efficiency, the type of amplifier element, and operating conditions. The present invention is based upon the power supply control scheme. In particular, a large DC current flows through the output amplifier of the power amplifier circuit even in the absence of input power.
The drawbacks of the conventional output power control circuits will be described with reference to FIGS. 1 to 4. Referring to FIGS. 1 to 4, reference numeral 1 denotes a preceding or input amplifier; 2, a succeeding or output amplifier through which a large current flows in the absence of input power; 3, an input terminal; 4, an output terminal; 5, a connecting point between the input amplifier 1 and the output amplifier 2; 6, a power supply terminal of the input amplifier 1; 7, a power supply terminal of the output amplifier 2; 8 and 9, power control transistors, respectively; 10, a control terminal; and 11, a DC power supply terminal. It should be noted that resistors for controlling the operating points of the control transistors 8 and 9 are omitted in FIGS. 1 to 4.
The power consumption of electronic equipment including a power amplifier is mainly determined by the power consumption of the power amplifier. In favor of low power consumption, a sum of power consumption of the power amplifier and that of the output power control circuit is preferably small, regardless of the coutput level. In the circuits shown in FIGS. 1 and 2, a control current of about 1/10 of a collector current of the transistor 9 or, a circuit current of the output amplifier must flow to the control terminal 10 so as to saturate the transistor 9 with a voltage drop due to a collector-emitter voltage V.sub.CE of the transistor 9 minimized when a maximum output is generated from the power amplifier circuit. This leads to an increase in current as a whole, thus degrading the efficiency of the entire circuit. However, when a Darlington amplifier is used as the transistor 9, it will do that a small current can flow to the control terminal 10. However, a voltage drop at the terminal 7 is great with the transistor 9 saturated, thereby decreasing the maximum output of the output amplifier 2 and hence resulting in inconvenience.
As described above, the output amplifier 2 comprises an amplifier through which a large current flows even in the absence of an input voltage. Assume that the output amplifier 2 serves as a complete class A amplifier. In this case, even if an input to the output amplifier 2 (i.e., the level at the connecting point 5) decreases and the output from the output amplifier 2 decreases, a DC current flowing through the output amplifier 2 will not change. It is otherwise assumed that the output amplifier 2 is operated such that a DC current flowing through the amplifier 2 upon delivery of a maximum output, i.e., upon reception of a large signal input is smaller than a current flow in the absence of an input signal. In this case, when the input decreases to decrease the output, the current increases and eventually becomes equal to that in the absence of an input signal. Conversely, when the amplifier is operated such that the current increases at the maximum output, the current initially decreases as the input decreases. However, when the amplifier is brought into a class A operation, the current eventually becomes steady, equalling the current in the absence of an input signal. In fine, when the input is controlled using the aforementioned output amplifier while the power supply voltage is kept constant, the efficiency is considerably degraded when the output is set to be greatly smaller than the maximum output.
The above drawback is illustrated in FIG. 5. Reference symbols P.sub.IN, P.sub.OUT, I and .eta. denote the input power, the output power, the DC current, and the power efficiency, respectively. Reference symbols a, b and c denote the aforementioned three operating states. Thus, the operating state a corresponds to the class A operating state, the operating state b corresponds to the state wherein the current decreases when a large input is received, and the operating state c corresponds to the state wherein the current increases when a large input is received. A power supply voltage V.sub.s is of course kept constant. In any one of these operating states, the folowing relations are given when the output is small corresponding to the input which is less than a level indicated by a dotted line d: EQU P.sub.OUT =k.sub.1 P.sub.IN, I=k.sub.2 EQU .eta.=(P.sub.OUT -P.sub.IN)/VsI=(k.sub.1 -1)P.sub.IN /k.sub.2 ( 1)
where k.sub.1 and k.sub.2 are constants, indicating that when the input decreases, the efficiency decreases proportionately.
On the other hand, FIG. 6 shows graphs for explaining the electrical characteristics under condition that the power supply voltage changes when the input power is kept at the maximum output. As is apparent from the graphs, the following relations can be established by approximation in most of the operating range: EQU P.sub.OUT =k.sub.3 V.sub.s.sup.2, I=k.sub.4 V.sub.s EQU .eta.=(P.sub.OUT -P.sub.IN)/V.sub.s I=k.sub.3 /k.sub.4 -P.sub.IN /k.sub.4 V.sub.s.sup.2 ( 2)
where k.sub.3 and k.sub.4 are constants. When k.sub.4 V.sub.s.sup.2 &gt;P.sub.IN is established, the efficiency will remain unchanged. In other words, when the power supply voltage is changed while maintaining the input at a predetermined level, the output power control can be effected without degrading the efficiency even at a low output. When the power supply voltage is kept at a very low level, the second term cannot of course be neglected with respect to the first term in equation (2), resulting in a degraded efficiency as indicated by a curve e. However, even the degraded efficiency can be much improved over the case in FIG. 5.
Strictly speaking, a decrease in the input to the output amplifier 2 means a decrease in the output from the input amplifier 1. In this case, a current flowing through the input amplifier 1 decreases, so that both an increase in current through the output amplifier 2 and a decrease in current through the input amplifier 1 must be considered for determination of the entire current. If, as in the typical case, the power amplification factor of the input amplifier 1 is about 10 dB and the amplifiers 1 and 2 have the same power efficiency, the current flowing through the input amplifier 1 may be decreased to a fraction or 1/10 of the current of the output amplifier 2. Furthermore, a change in current of the output amplifier 2 is greater than that of the input amplifier 1. Under these conditions, in order not to degrade power efficiency at a low output level, it is most effective to change the power supply voltage of the output amplifier without decreasing the input supplied to the output amplifier below a given level.
From the viewpoint described above, the circuit arrangement shown in FIG. 3 is not preferable, as compared with the circuit arrangement shown in FIG. 2. However, the circuit shown in FIG. 2 presents the problem of the current flowing to the control terminal 10, as previously described. In order to overcome the drawbacks of the circuit arrangements shown in FIGS. 2 and 3, a circuit shown in FIG. 4 can be conceived. In this circuit arrangement the input and output amplifiers 1 and 2 appear to be properly controlled to provide a good power efficiency. However, the transistor 9 is completely saturated, so that the transistor 8 comes close to the cut-off state at a base current of the transistor 9 (i.e., collector current of the transistor 8) which brings this transistor 9 into active state. As a result, the conditions for a decrease in the output are already satisfied. Therefore, the current at a very small output is substantially the same as that in the circuit arrangement in FIG. 3. Even if resistors are arranged to control the operating points of the transistors 8 and 9, much improvement cannot be expected.
As described above, according to the conventional methods, the control current is increased at the maximum output, thereby degrading the efficiency. The decrease in DC current is slight when the output is set to be lower than the maximum output, thereby degrading the efficiency. These two drawbacks cannot both be improved at the same time, even if one of them can be improved.